The Latch macro (combining Read and Write modules) is available from
Library -> Memory -> Latch.
It will read a value from upper input.
Only when the lower input changes, does the upper value go to the output.
The Core Cell structure:
The primary structure view:
The panel view shows upper (x) = out (since lower value (a) is changing):
We can find the x div a macro in Library -> Math Mod -> x div a.
While the / module will divide at once, the x div a macro will wait until
x changes.
This is shown by comparing the two. The two output only match when
x changes. Thus when a is changing, only the / output changes.
The core cell structure:
The primary structure:
The panel view showing a changing leading to difference in outputs:
We can find the x mul a macro in Library -> Math Mod -> x mul a.
While the * module will multiply at once, the x mul a will wait until
x changes.
This is shown by comparing the two. The two output only match when
x changes. Thus when a is changing, only the * output changes.
The core cell structure:
The primary structure:
The panel view showing a changing leading to difference in outputs:
The last example provides the argument for different oscillators.
Here we will drive it through a sine macro, which is available from
Library -> Math -> Trig-Hyp -> sin.
The sine macro is added to the end, before the Out output port. You can double click the sine macro
to see the structure, and keep on double clicking any nested macros.
The Core Cell structure:
The primary structure view showing now the scope is from -1 to +1:
The panel view:
The last example was bound by 1. Now this example is bound by pi. However the lower value is not zero, but -pi.
We create 2 QuickBuses, with a value of pi and 2*pi.
Note that we have added a * module near the Freq input with a value
of 2*pi. In the last example the range was 1, thus it was same as multiplication
by 1. However now the range is 2*pi, and thus we have to multiply with
this value, so the time period is consistent.
We use a Compare module to see if the latch value is above pi. If it is, it will be
subtracted by 2*pi to go back to minus pi.
The Core Cell view:
The primary structure view with a scope from -pi to pi over 1
millisecond:
The Panel view:
In the last example the output kept on increasing. Here the upper
bound is 1.
The output starts at zero, and at each sampling rate clock, increases
by Freq/SR, where SR is usually 44100.
A Compare module will see if it is above 1. If so, it will go to
the upper router output and have a value of 1 subtracted, thus it should
be back at 0.
The counter value from the two cases (either less than 1 or subtracted
by 1) are merged and fed into the Write module.
Thus the value from the merge is always a value between 0 and 1.
In the primary structure, we connect the Core Cell output to a Scope.
The Scope will show a 1 millisecond signal from -1 to +1.
The core cell structure:
The primary structure:
The panel view:
Now we do not use a Clock oscillator from the primary structure.
Instead we use the sample rate clock (right-click on clock terminal
and select Pickup Standard Distribution Bus, and then Pickup SR.C).
Since the sample rate clock increases ticks 44100 times per second,
we have to have to add 1 divided by 44100 each time. Thus now the output
will be in seconds. If the Freq is 2, rather than 1, it will increase twice
as fast and so on. We can get the sample rate as SR.R from the Std. Distribution Bus.
Usually the Sample Rate will be 44100.
We also have changed the output Cnt as Audio rate signal rather than control rate
using the Properties Sidebar.
The Core Cell structure:
The primary structure view:
The panel view:
