Core 10. Ramp oscillator

In the last example the output kept on increasing. Here the upper bound is 1.

The output starts at zero, and at each sampling rate clock, increases by Freq/SR, where SR is usually 44100.

A Compare module will see if it is above 1. If so, it will go to the upper router output and have a value of 1 subtracted, thus it should be back at 0.

The counter value from the two cases (either less than 1 or subtracted by 1) are merged and fed into the Write module.

Thus the value from the merge is always a value between 0 and 1.

In the primary structure, we connect the Core Cell output to a Scope. The Scope will show a 1 millisecond signal from -1 to +1.

The core cell structure:

The primary structure:

The panel view: