Core 7. Reset of Counter using Merge

A Clock Oscillator with a Frequency F is connected to Inc input of the Core Cell.

For the Core Cell, Inc is the clock to start Read operation sending latch value to + module which adds 1. Thus we add 1 each time we have an event.

The + module output is merged with the Reset signal, and sent to Write.

The Reset signal is a button, in the primary structure. The On and Off values both are 0, so a 0 event is sent whenever Reset button is clicked.

A knob Freq has properties Min of 1, Max of 10, and Step Size of 1. We divide Freq by 2 so the number of events is at a rate of Freq.

The Cnt value of the Core Cell is read by a Numeric Readout.

The core cell structure:

The primary structure:

The panel view: